1. Technical Field
The present invention relates to a sampling clock selection module for a serial data stream.
2. Related Art
When high speed serial data are transmitted, data jitter or phase skew of the data relative to a clock signal will significantly reduce a sampling interval of a valid bit. FIG. 1 is an eye diagram of a typical high speed serial data stream. In FIG. 1, a sampling interval of a valid bit, i.e., an interval where the data bit is stable, is shorter than a width T of the bit. Moreover, if variations in a fabrication process, an operating temperature and a supply voltage of the circuit are taken into consideration, the sampling interval of the valid bit is further reduced, lowering an accuracy of the sampled data bit.
A direct method to solve the foregoing problem is to perform oversampling on the received serial data stream. FIG. 2 is a schematic diagram illustrating a conventional three-times oversampling. The operation of three-times oversampling involves performing sampling on data bits in the serial data stream with a clock having a frequency three times the data bit rate. Next, an exclusive-or (XOR) operation is performed on every two adjacent sampled data states and then calculation is performed by a digital circuit to obtain edge information of the data bit.
However, when the conventional three-times oversampling method is employed, three sampling circuits are required to obtain data states in response to the respective sampling clocks. If a higher accuracy of the sampled data bit is desired, more sampling circuits have to be used, which significantly increase the circuit cost and design complexity.
Therefore, it is highly desirable to provide an improved sampling clock selection module for a serial data stream.